2.5.3 Digital Output Pins
As long as the P_ON pin is high, all digital output pins operate as described. If the P_ON
pin is low, all digital output pins are switched to high impedance mode.
The digital outputs PP0, PP1, PP2 and PP3 are configurable, where each of the signals
CLK_OUT, RX_RUN, NINT, a LOW level (GND) and a HIGH level, DATA,
DATA_MATCHFIL, CH_DATA, CH_STR, RXD and RXSTR can be routed to any of the
four output pins. There is only one exception, CLK_OUT is not available on PP3. The
default configuration for these four output pins can be seen in Table 1.
Each port pin can be inverted by usage of PPCFG2 register.
The RX_RUN signal is active high for all Configurations by default. It can be deactivated
for every Configuration separately. Every PPx can be configured with an individual
RX_RUN setup. This can be set in RXRUNCFG0 and RXRUNCFG1 registers.
Interfacing to 3.3V Logic:
The TDA5235 is able to interface directly to a 3.3V logic, when chip is operated in 3.3V
environment.
Interfacing to 5V Logic:
The TDA5235 is able to interface directly to a 5V logic, when chip is operated in 5V
environment.
EMC Reduction of Digital I/Os:
Because electromagnetic distortion generated by digital I/Os may interfere with the high
sensitivity radio receiver, it is recommended that all inputs are filtered by adding an RC
low pass circuit.